- 您现在的位置：买卖IC网 > Sheet目录395 > ATMEGA128RFA1-ZUR (Atmel)IC AVR MCU 2.4GHZ XCEIVER 64QFN
ATmega128
TWI Data Register –
TWDR
Bit
Read/ W rite
Initial Value
7
TWD7
R/ W
1
6
TWD6
R/ W
1
5
TWD5
R/ W
1
4
TWD4
R/ W
1
3
TWD3
R/ W
1
2
TWD2
R/ W
1
1
TWD1
R/ W
1
0
TWD0
R/ W
1
TWDR
In Transmit mode, T W DR contains the next byte to be transmitted. In receive mode, the T W DR
contains the last byte received. It is writable while the T W I is not in the process of shifting a byte.
This occurs when the T W I interrupt flag (T W INT) is set by hardware. Note that the Data Register
cannot be initialized by the user before the first interrupt occurs. The data in T W DR remains sta-
ble as long as T W INT is set. W hile data is shifted out, data on the bus is simultaneously shifted
in. T W DR always contains the last byte present on the bus, except after a wake up from a sleep
mode by the T W I interrupt. In this case, the contents of T W DR is undefined. In the case of a lost
bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is
controlled automatically by the T W I logic, the CPU cannot access the ACK bit directly.
? Bits 7..0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the Two-wire Serial Bus.
TWI (Slave) Address
Register – TWAR
Bit
Read/ W rite
Initial Value
7
TWA6
R/ W
1
6
TWA5
R/ W
1
5
TWA4
R/ W
1
4
TWA3
R/ W
1
3
TWA2
R/ W
1
2
TWA1
R/ W
1
1
TWA0
R/ W
1
0
TWGCE
R/ W
0
TWAR
The T W AR should be loaded with the 7-bit slave address (in the seven most significant bits of
T W AR) to which the T W I will respond when programmed as a slave transmitter or receiver, and
not needed in the master modes. In multimaster systems, T W AR must be set in masters which
can be addressed as slaves by other masters.
The LSB of T W AR is used to enable recognition of the general call address ($00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
? Bits 7..1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the T W I unit.
? Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.
Using the TWI
The AVR T W I is byte-oriented and interrupt based. Interrupts are issued after all bus events, like
reception of a byte or transmission of a START condition. Because the T W I is interrupt-based,
the application software is free to carry on other operations during a T W I byte transfer. Note that
the T W I Interrupt Enable (T W IE) bit in T W CR together with the Global Interrupt Enable bit in
SREG allow the application to decide whether or not assertion of the T W INT flag should gener-
ate an interrupt request. If the T W IE bit is cleared, the application must poll the T W INT flag in
order to detect actions on the T W I bus.
W hen the T W INT flag is asserted, the T W I has finished an operation and awaits application
response. In this case, the T W I Status Register (T W SR) contains a value indicating the current
state of the T W I bus. The application software can then decide how the T W I should behave in
the next T W I bus cycle by manipulating the T W CR and T W DR Registers.
Figure 95 is a simple example of how the application can interface to the T W I hardware. In this
example, a master wishes to transmit a single data byte to a slave. This description is quite
207
2467X–AVR–06/11
发布紧急采购，3分钟左右您将得到回复。
相关PDF资料
ATMEGA64RZAPV-10AU
BUNDLE ATMEGA644P/AT86RF230 TQFP
ATP101-TL-H
MOSFET P-CH 30V 25A ATPAK
ATP102-TL-H
MOSFET P-CH 30V 40A ATPAK
ATP103-TL-H
MOSFET P-CH 30V 55A ATPAK
ATP104-TL-H
MOSFET P-CH 30V 75A ATPAK
ATP106-TL-H
MOSFET P-CH 40V 30A ATPAK
ATP107-TL-H
MOSFET P-CH 40V 50A ATPAK
ATP108-TL-H
MOSFET P-CH 40V 70A ATPAK
相关代理商/技术参数
ATMEGA128RFA1-ZUR SL514
制造商:Atmel Corporation 功能描述:
ATMEGA128RFA1-ZUR00
制造商:Atmel Corporation 功能描述:2.4GHZ 802.15.4 128K SOC REVF 制造商:Atmel Corporation 功能描述:2.4GHZ 802.15.4 128K SOC REVF T&R - Bulk 制造商:Atmel from Components Direct 功能描述:ATMEL ATMEGA128RFA1-ZUR00 MICROCONTROLLERS (MCU) 制造商:Atmel 功能描述:Atmel ATMEGA128RFA1-ZUR00 Microcontrollers (MCU) 制造商:Atmel Corporation 功能描述:MCU AVR 2.4GHZ 128K FLASH 64VQFN 制造商:Atmel Corporation 功能描述:2.4GHZ 802.15.4 128K SOC Revision F 制造商:Atmel 功能描述:2.4GHZ 802.15.4 128K SOC REVF
ATMEGA128RFR2-ZF
功能描述:IC RF TXRX+MCU 802.15.4 64-VFQFN 制造商:microchip technology 系列:- 包装:托盘 零件状态:在售 类型:TxRx + MCU 射频系列/标准:802.15.4 协议:Zigbee? 调制:DSSS， O-QPSK 频率:2.4GHz 数据速率（最大值）:2Mbps 功率 - 输出:3.5dBm 灵敏度:-100dBm 存储容量:128kB 闪存，4kB EEPROM，16kB SRAM 串行接口:I2C，JTAG，SPI，USART GPIO:35 电压 - 电源:1.8 V ~ 3.6 V 电流 - 接收:5mA ~ 12.5mA 电流 - 传输:8mA ~ 14.5mA 工作温度:-40°C ~ 125°C 封装/外壳:64-VFQFN 裸露焊盘 标准包装:260
ATMEGA128RFR2-ZU
制造商:Atmel Corporation 功能描述:2.4GHZ 802.15.4 128K SOC IND 85C - Bulk
ATMEGA128RFR2-ZUR
制造商:Atmel Corporation 功能描述:2.4GHZ 802.15.4 128K SOC 85C T&R - Tape and Reel
ATMEGA128RZAV-8AU
功能描述:射频微控制器 - MCU AVR Z-Link Bundle RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:Si100x 数据总线宽度:8 bit 最大时钟频率:24 MHz 程序存储器大小:64 KB 数据 RAM 大小:4 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LGA-42 安装风格:SMD/SMT 封装:Tube
ATMEGA128RZAV-8MU
功能描述:射频微控制器 - MCU AVR Z-Link Bundle RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:Si100x 数据总线宽度:8 bit 最大时钟频率:24 MHz 程序存储器大小:64 KB 数据 RAM 大小:4 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LGA-42 安装风格:SMD/SMT 封装:Tube